Method of an array of structures sensitive to ESD and structure made therefrom

ABSTRACT

A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 93104404, filed on Feb. 23, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a thin filmtransistor (TFT) array, and more particularly to a method of fabricatingan array of structures sensitive to electrostatic discharge andstructure made therefrom.

2. Description of the Related Art

Because of its low operational voltage, non-radiation, small weight andsize superior to those of cathode ray tube (CRT), liquid crystaldisplay, plasma display and electroluminance display have been widelystudied and developed, and is viewed as the main stream display in thefuture.

Active matrix liquid crystal display controls data read/write by activeelement such as transistors or diodes at pixel, for example, TFT liquidcrystal display. When the transistor is on, the signal is transmitted tothe pixel; whereas when the transistor is off, the capacitor canmaintain a potential to drive the liquid crystal. Therefore, the liquidcrystal within such driving period is in a static state.

Electrostatic discharge (ESD) is always a big problem with thefabrication of TFT. Electrostatic charges may build up at any time andany place, such as, during the manufacturing, transportation, storageand usage of the digital electronic devices. Should the electrostaticcharges discharge onto the TFT, it would cause arcing, release of asurge of energy, and/or a momentary current and/or voltage surge, whichcould damage the TFT structure. How to resolve the problem of ESD and toenhance the manufacturing yield is important.

SUMMARY OF THE INVENTION

The present invention provides a solution to avoiding damages from ESDduring substrate processing. The individual structures formed on thesubstrate are initially conductively coupled together byinterconnections as the structures are being formed. Electrostaticcharges built up in the structures on the substrate are dischargeautomatically before damage can be done. The interconnections betweenthe individual structures are removed before fabricating another arrayof structures.

The present invention also discloses an array substrate including asubstrate and an array of structures formed on the substrate, whereinthe structures are initially conductively coupled by interconnections,but the interconnections are removed before the fabrication of anotherarray of structures.

The present invention resolves the problem of electrostatic discharge byimproving the fabrication processes. First, independent circuits of aconductive layer are designed to have equal potential. Further, pointdischarge structures are formed on the edges of the substrate.Therefore, in accordance to the present invention, the prevention fromelectrostatic discharge is enhanced during the entire manufacturingprocess. Consequently, the manufacturing yield is improved.

In order to make the aforementioned and other aspects, features andadvantages of the present invention understandable, a preferredembodiment accompanied with figures is described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating the process flow of fabricating anexemplary TFT array in accordance with one embodiment of the presentinvention.

FIG. 2 is a schematic circuit layout generated from the step 104 of theprocess flow for fabricating the TFT array of FIG. 1.

FIG. 3( a) is a schematic circuit layout generated from the step 106 ofthe process flow for fabricating the TFT array of FIG. 1; and FIG. 3( b)is a cross-section drawing of portion of the TFT array in FIG. 3( a).

FIG. 4( a) is a schematic structure showing an exemplary TFT array.

FIGS. 4( b) and (c) are enlarged schematic drawings of part IV in FIG.4( a).

FIG. 5 is a display device that incorporates the TFT array fabricated inaccordance with the present invention.

FIG. 6 is an electronic device that incorporates a display device havingthe TFT array fabricated in accordance with the present invention.

DESCRIPTION OF SOME EMBODIMENTS

FIG. 1 is a flow chart illustrating the process flow of fabricating anexemplary TFT array of the present invention. The conductive layer isformed by two photolithographic processes and etching processes. Eachphotolithographic process includes for example, the steps of photoresistcoating, soft bake, hard bake, exposure, fixing, development, andetching to pattern the conductive layer.

Referring to FIG. 1, a substrate is provided in step 100, which is atransparent substrate, such as, a glass substrate or quartz substrate.In step 102, a conductive layer is formed on the substrate.

In step 104, a first photolithographic process is performed for forminga patterned conductive layer, which comprises a plurality of independentcircuits and interconnections connecting the independent circuits (seealso FIG. 2). Furthermore a point discharge structure can be formed onthe edge of the substrate simultaneously (see also FIG. 4). The pointdischarge structure can reduce electric potential of the substrate bysharing out and decreasing the electrostatic potential that is inducedand accumulated from environment, without interfering with the maincircuits of the TFT array.

Referring to FIG. 1, a second photolithographic process is performed toremove the interconnections of the conductive layer in step 106 beforeforming next conductive layer (see also FIG. 3( a)). Then, an insulatinglayer is formed on the conductive layer in step 108, which can be, forexample, a dielectric layer. After step 108, the step 102 can berepeated for forming next conductive layer.

When the present invention is applied to the fabrication of a TFT array,the layers formed by lithography processes in FIG. 1 may include a firstmetal layer (e.g. gate, scan line, etc.) and a second metal layer(source, drain, data line, etc.) Specifically, referring to FIG. 3( b),several polysilicon islands 302 are formed on a substrate 300 and thenan insulating film 304 is provided to cover the polysilicon islands 302.Next, a gate 202 can be formed on each of polysilicon islands 302 inaccordance with steps 102˜106. An insulating layer (not shown) is formedover the resulting structure in FIG. 3( b) as a protective layer in step108.

Then, the steps 102˜106 are repeated for the other layers of the TFT.More specifically, in the illustrated embodiment, a second conductivelayer is formed over the underlying structure. In a step similar to step104, the second conductive layer is patterned for forming independentcircuits, which comprises source/drain and data lines connected tosource/drain, and interconnections connected to the above mentionedindependent circuits. In a step similar to step 106, theinterconnections of the second conductive layer then are removed. Asecond insulating layer is formed over the second conductive layer forevenness in step a step similar to 108, wherein the second insulatinglayer has a plurality of contact holes. Pixel electrodes are formed onthe second conductive layer and electrically connect to the source/drainterminals of the second conductive layer through the contact holes.

The difference between the first and the second photolithographicprocesses is illustrated below.

FIG. 2 and FIG. 3 are schematic circuit layouts generated from the steps104 and 106 of the process flow for fabricating the TFT array,respectively. Please referring to FIG. 2, it is a pattern 200 of theconductive layer after the first photolithographic process, whichcomprises independent circuits 202 and interconnections 204 connectingthe independent circuits 202. The pattern 200 of the conductive layer isnot limited thereto. In addition, it is also desirable that theinterconnections 204 and the independent circuits 202 are electricallyconnected within the pattern 200. Therefore, the two-row independentcircuits as shown in FIG. 2 can be connected by one interconnection.

Please referring to FIG. 2, the pattern 200 of the conductive layerformed by the first photolithographic process makes the conductive layerhave equal potential. Therefore, there is no local electrostaticdischarge and arc phenomenon occur from the high potential difference inthe same layer.

Please referring to FIG. 3( a), the interconnections 204 connecting theindependent circuits 202 are removed and the independent circuits 202are remained before forming the second conductive layer.

Following are the descriptions of forming an electrostatic dischargeprotection structure.

FIG. 4( a) is a schematic diagram showing the structure of an exemplaryTFT array. FIGS. 4( b) and (c) are enlarged schematic drawings of partIV in FIG. 4( a). Please referring to FIGS. 4( a)-(c), the electrostaticdischarge protection structure of the present invention can be formed atthe edge of the substrate 400 in steps 102˜104 of forming the patternedconductive layer, which comprises two tips 404, wherein the two tips 404face or mismatch from each other without connection. In addition, eachtip connects to one of two conductive wires that are isolated from eachother. The method of fabricating the two tips 404 may includes providinga first tip conductively coupled to the array of structures as shown inFIG. 3( a) and then providing a second tip grounded, whereinelectrostatic charges can be discharged from one tip to the other.Because the point discharge structure is formed on the edge of thesubstrate 400, the electric potential of the substrate 400 is reduced bysharing out and decreasing the electrostatic potential that is inducedand accumulated from environment without interfering with the TFT 402.

In the present invention, all conductive layers have equal potential andthe electrostatic discharge protection structure is formed on the edgeof the substrate. Therefore, there is no partial electrostatic dischargeand arc phenomenon occur from the high potential difference in the samelayer during follow-up processes. And, electrostatic discharge damage tothe conductive layers of the substrate can be eliminated by means of thepoint discharge structure by sharing out and decreasing theelectrostatic potential that is induced and accumulated fromenvironment. Moreover, before forming next conductive layer, theinterconnections of the conductive layer are removed and the nextconductive layer can follow the same design to prevent electrostaticdischarge. Thus, the present invention can cooperate with other devicesand processes and is not limited thereto.

FIG. 5 is a display device that incorporates the TFT array fabricated inaccordance with the present invention. Referring to FIG. 5, a displaypanel 1 is provided and an array of TFT of the display panel 1 is formedin accordance with the steps in FIG. 1. Besides, a controller 2 isconnected with the display panel in order to control the display panel.

FIG. 6 is an electronic device that incorporates a display device 3having the TFT array fabricated in accordance with the presentinvention. Referring to FIG. 6, an input device 4 is coupled to thecontroller 2 of the display device 3 shown in FIG. 5 can include aprocessor or the like to input data to the controller 2 to render animage. The electronic device 5 may be a portable device such as a PDA,notebook computer, tablet computer, cell phone or a desktop computer.

Although the present invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be constructed broadly to include other variants and embodimentsof the invention which may be made by those skilled in the field of thisart without restructuring from the scope and range of equivalents of theinvention. For example, ESD protection need not be provided for each andevery layers shown in FIG. 3. ESD protection in accordance with thepresent invention may be omitted for those layers in which thestructures are less sensitive to ESD. Further, the various conductivelayers and/or insulating layers may each comprise more than one type ofmaterial or sublayer processes by each step shown in FIG. 1. The actualfabrication process may also include additional initial, intermediateand/or later steps not shown in the flow diagram shown in FIG. 1.

1. A method of fabricating on a substrate, an array of structuressensitive to ESD, comprising: providing an electrostatic dischargestructure near the periphery of the substrate; forming the array ofstructures on the substrate, with the structures being conductivelycoupled by interconnections in a manner such that the array ofstructures are at same potential, wherein the array of structures isconductively connected to the electrostatic discharge structure forelectrostatic protection without directly connecting each structure inthe array of structures to the electrostatic discharge structure; andconductively decoupling the array of structures to separate thestructures conductively.
 2. The method as in claim 1, wherein the arrayof structures each comprises an individual circuit.
 3. The method as inclaim 1, wherein the array of structures comprises an array of TFT. 4.The method as in claim 1, wherein the step of providing theelectrostatic discharge structure comprises: providing a first tipconductively coupled to the array of structures; and providing a secondtip grounded, wherein electrostatic charges can be discharged from onetip to the other.
 5. The method as in claim 4, wherein the first tip andthe second tip are facing or mismatching from each other withoutconnection.
 6. The method as in claim 1, wherein the step of forming thearray of structures on the substrate comprises: forming a firstconductive layer on the substrate; and patterning the first conductivelayer to form the array of structures and the interconnections withinthe first conductive layer.
 7. The method as in claim 1, wherein theelectrostatic discharge structure is provided by forming theelectrostatic discharge structure during the step of forming the arrayof structures.
 8. The method as in claim 6, further comprising: forminga second conductive layer above the first conductive layer after thearray of structures have been conductively decoupled.
 9. The method asin claim 8, wherein the step of forming the second conductive layerincludes providing an insulating layer on the first conductive layerprior to forming an array of structures in the second conductive layer.10. The method of claim 1, wherein the step of conductively decouplingthe array of structures includes conductively breaking theinterconnections.
 11. The method of claim 10, wherein the step ofconductively breaking the interconnections includes removing theinterconnections.
 12. The method of claim 6, wherein the array ofstructure comprises a plurality of independent circuits, and theinterconnections connect the plurality of independent circuits.
 13. Themethod of claim 12, wherein the plurality of independent circuits andthe plurality of interconnections are of the same conductive material inthe first conductive layer.